1. Field of the Invention
The present invention relates to fabrication of integrated circuit devices and, more particularly, to a method of forming a gate structure on a semiconductor device, such as a field effect transistor.
2. Description of the Related Art
The manufacturing process of integrated circuits involves the fabrication of numerous insulated gate field effect transistors, such as metal oxide semiconductor field effect transistors (MOSFET). In order to ever increase integration density and improve device performance, for instance with respect to signal processing time and power consumption, feature sizes of the transistor structures are steadily decreasing. Accordingly, there is a demand for ever-improved, efficient, reliable and inexpensive methods for patterning the various process layers or films in an integrated circuit device so as to be suitable for the needs of mass production. Optical photolithography is generally used as the standard method for feature definition in semiconductor manufacturing operations. This process generally provides the desired high throughput. With currently available photolithography steppers, using high NA (numerical aperture) lenses and deep UV (ultraviolet) exposure light and a subsequent etch-trim process, it is, for instance, possible to reliably pattern feature sizes as small as 0.2 .mu.m.
As will be understood by those skilled in the art, the formation of a gate electrode of a semiconductor device is a critical step in the manufacturing process of the device. The gate length dimension, i.e., the lateral extension of the gate electrode between the source and the drain electrode of a transistor, is desirably reduced to sizes approaching or even exceeding the resolution limit of the optical imaging systems used for patterning the device features. In a field effect transistor, such as a MOSFET, the gate electrode is used to create and control an underlying channel which forms near the surface of the semiconductor substrate between a source region and a drain region once the voltage supplied to the gate electrode exceeds the threshold voltage of the transistor.
The source and the drain regions are formed in, on or over the semiconductor substrate, which is doped inversely to the drain and source regions. The gate electrode is separated from the channel and the source and drain regions by a thin insulating, gate dielectric layer, that is generally comprised of an oxide layer or a nitride layer. During operation, a voltage is supplied to the gate electrode in order to create an electric field which, in turn, generates an inversion layer near the surface of the substrate below the thin insulating, gate dielectric layer. The electric field controls the conductivity as well as the depth of the inversion layer which provides for an electrical connection between the source and drain. Thus, it is desirable to have a thin gate dielectric layer to enhance the electric field for rapidly building up a deep inversion layer to attain improved signal performance of the transistor device. In this respect, it is also desirable to have as short a channel length as possible to further reduce the resistance of the transistor, and increase the overall operating speed of the device.
An illustrative example of forming a gate electrode according to a typical prior art process will be described with reference to FIGS. 1A-1C which show schematic cross-sectional views of various stages in the formation of the gate structure of a typical prior art device. As the skilled person will readily appreciate, these figures are merely of an illustrative nature and are provided only to facilitate the explanation of various process steps. Accordingly, the relation between various feature sizes may not necessarily reflect the real situation. In addition, in reality, boundaries between specific portions of the device and between various layers may not be as sharp and precise as illustrated in these figures.
FIG. 1A shows a schematic cross-sectional view in which shallow trench isolations 2 comprised of silicon dioxide are formed in a silicon substrate 1. Between the shallow trench isolations 2, which define an active region 20 of the transistor device to be formed, a thin gate oxide layer 3 has been grown. Subsequently, a gate electrode material layer 4 consisting of, for example, polycrystalline silicon, has been deposited over the structure. The gate electrode layer 4 is covered by an anti-reflective coating (ARC) layer 5. The ARC layer 5 is used to perform an advanced DUV-photolithography step in order to produce a gate electrode resist mask 6 over the gate electrode layer 4. Creating the gate electrode resist mask 6 using DUV photolithography techniques, as well as a critical etch trim process used to form the resist mask 6, is cost-intensive and may also lead to large variations in the gate lengths and thus large variations in performance of the resulting semiconductor device may result.
FIG. 1B depicts a schematic view of the device as shown in FIG. 1A after a portion of the ARC layer 5 and a portion of the gate electrode layer 4 have been removed by anisotropic etching, wherein the resist mask 6 serves as an etch mask to form a gate electrode 4A.
FIG. 1C schematically shows the finally-completed device, wherein the following steps have been performed. The resist mask 6, shown in FIG. 1B, has been stripped off and the ARC layer 5 has been removed by one or more wet chemical etching processes. Subsequently, lightly doped regions are formed in the substrate 1, and a plurality of sidewall spacers 7 serve as an implantation mask for the subsequent implantation step for the formation of a drain and a source region 8. Then, a rapid thermal annealing process is performed to activate the drain and source regions 8, and a silicide processing operation is performed to produce drain and source electrodes 9.
As discussed above, the length of the gate electrode 4A is defined by the resist mask 6, which is formed by a DUV photolithographic step, and the subsequent etching of the gate electrode layer 4. If the gate length dimension is reduced to less than a size which can be reliably patterned by conventional photolithography techniques, the use of highly-sophisticated DUV technology, which is cost-intensive, and the necessary etch-trim process, leads to variations in the gate lengths of devices fabricated on different substrate wafers or at different locations within a single wafer, or to variations in the gate length along a gate width direction, which is defined by the extension of the transistor in the direction perpendicular to the drawing plane of FIGS. 1A-1C. These variations, in turn, result in strongly varying drive currents and, accordingly, in strongly varying electrical characteristics of the transistors.
Therefore, as the dimensions of the gate electrode 4A significantly influence the electrical characteristics of the transistor, it is important to provide a method of reliably and reproducibly patterning gate electrodes 4A so as to minimize variations in the electrical characteristics of integrated circuits. Formation of gate electrodes beyond the sub-quarter micron range, to the extent to which this is even possible, conventionally requires especially costly and complex patterning processes using the most up-to-date patterning tools such as the aforementioned deep ultraviolet (DUV) photolithography steppers.
In view of the above-described problems, a need exists for a method of patterning gate electrodes of field effect transistors in integrated circuits to a size smaller than the resolution limit of currently available photolithography tools.
The present invention is directed to a method of making a semiconductor device that solves, or at least reduces, some or all of the aforementioned problems.